A digital video interface is a standard being used for a number of video applications that require high frequency video data transmission from one integrated circuit board to another. The digital video interface standard uses transition minimized differential signals to accomplish this task.
Conventionally, the digital video interface transmitter encodes the data that is sent to a digital video interface receiver to reduce electromagnetic interference. The encoding is done to reduce the occurrence of high frequency transitions that would lead to increased electromagnetic interference levels.
Although the use of a digital video interface transmitter and a digital video interface receiver reduce electromagnetic interference, there is no standard digital video interface transmitter or digital video interface receiver, thereby creating a multitude of different devices that operate differently from the other. Due to these variations in the currently available digital video interface transmitters and/or digital video interface receivers, it has become very difficult to design a system, in particular, a receiver that is compatible (error free) with all the available transmitters.
The digital video interface standard defines an operating bandwidth for the transmitter and receiver to follow. However, there are transmitters that operate at the edge of the standard, possibly falling outside of this bandwidth definition. Transmitters that operate in these regions often create jitter patterns that a receiver operating within the digital video interface standard cannot track. When the receiver cannot track the jitter of the data, errors will occur during the data recovery process.
Generally, a conventional digital video interface transmitter sends three transition minimized differential data signals and a transition minimized differential clock signal to a digital video interface receiver. The conventional digital video interface receiver incorporates a data recovery algorithm to correctly acquire the data. The conventional digital video interface transmitter uses an internally generated phase lock loop (PLL) clock signal to latch out the data. This data along with a clock signal is sent to the conventional digital video interface receiver. The digital video interface receiver creates a clock signal derived from the transmitted clock signal to latch in the data.
Conventionally, two basic clock techniques have been used in conventional digital video interface transmitters to send the clock to the digital video interface receiver. The most common and practical way is to send a clock signal that has been generated by the same phase lock loop which latched out the data (or one that has been divided down from that phase lock loop). This will help to ensure that the clock signal and data are synchronous/coherent and have the same jitter characteristics. An example of such a conventional technique is illustrated in FIG. 1.
As illustrated in FIG. 1, the conventional digital video interface transmitter receives data. The data is then latched out from a latch 10. The data is latched out from the latch 10 in response to a clock signal from a phase lock loop circuit 50. The phase lock loop circuit 50 also creates a clock signal that is transmitter to a digital video interface receiver.
The latched out data, of FIG. 1, has the same jitter characteristics as the phase lock loop circuit 50, and the clock signal that is sent to the receiver also has the same jitter characteristics. As long as the bandwidth of the receiver's phase lock loop circuit 40 can track this jitter, data from the digital video interface transmitter should be latched in correctly by latch 30.
Another conventional way to send the clock signal to the digital video interface receiver is illustrated in FIG. 2. As illustrated in FIG. 2, the conventional digital video interface transmitter transmits the clock signal before it goes through the transmitter's phase lock loop circuit 20
Moreover, as illustrated in FIG. 2, the conventional digital video interface transmitter receives data. The data is then latched out from a latch 10. The data is latched out from the latch 10 in response to a clock signal from a phase lock loop circuit 20. This technique does not ensure that the data and clock signal are synchronous/coherent, causing the data and clock signal to have different jitter patterns and making it more difficult for the conventional digital video interface receiver to acquire the correct data.
For this technique, as illustrated in FIG. 2, to work successfully the conventional digital video interface receiver must understand the properties of the transmitter's phase lock loop circuit 20. The jitter of the data leaving the transmitter is highly based on the transmitter's phase lock loop circuit 20 transfer function.
The problem with this technique can be seen by the illustrations of FIGS. 3 through 5. As illustrated in FIG. 3, the frequency of a typical clock signal utilized by a digital video interface transmitter includes jitter. The frequency of the clock signal is fN. The jitter is represented by the spread of the trace around the frequency of the clock signal (A). The jitter is shown by the arrows. If there was no jitter in the signal, the trace would be a single peak at the frequency of the clock signal, fN, with no spread.
This clock signal is processed by a phase lock loop circuit having a transfer function, H(s), illustrated in FIG. 4. The clock signal is convoluted with the transfer function, H(s), in phase lock loop circuit to produce the signal as illustrated in FIG. 5. The convoluted signal includes an unwanted or unpredictable jitter represented by B. The unwanted or unpredictable jitter is transferred to the data being latched.
If the clock signal of FIG. 3 is transmitted directly to the digital video interface receiver's phase lock loop circuit, this signal will not include information associated with unwanted or unpredictable jitter represented by B of FIG. 5. The received data will have been processed with this unwanted or unpredictable jitter, but the digital video interface receiver's phase lock loop circuit will be unaware of such a situation due to the absence of this information in the transmitted clock signal prior to it being processed by the digital video interface transmitter's phase lock loop circuit.
Thus, the digital video interface receiver's phase lock loop transfer function will be different from the digital video interface transmitter's phase lock loop transfer function, causing unwanted errors, based upon the differences in transfer functions, and loss of data
In an ideal situation, the phase lock loop circuit should have a small amount of jitter, relative to the input clock and its operating frequency. However, for certain digital video interface transmitter designs the phase lock loop design is done such to add unwanted jitter to the latched out data. This dependency will cause each phase lock loop transmitter design to have a slightly different transfer function. If the clock that is sent to the digital video interface receiver does not go through the phase lock loop, the jitter pattern of the data cannot be predicted.
For the digital video interface receiver to be most effective in receiving the correct data, the transfer function on the digital video interface receiver's phase lock loop should match the digital video interface transmitter's phase lock loop transfer function. This will allow the reference clock that goes into the phase lock loop in the digital video interface transmitter to go through the same phase lock loop on the digital video interface receiver, thus creating a matching transfer function.
However, since different manufactures of digital video interface transmitters will have a different phase lock loop architecture, one phase lock loop design for a digital video interface receiver may not be robust enough to track all digital video interface transmitters. If the digital video interface receiver's phase lock loop transfer function is different, unwanted errors may occur based upon the differences in transfer functions. The errors will produce loss of data.
Therefore, it is desirable to provide a digital video interface receiver that is compatible with any digital video interface transmitter. Moreover, it is desirable to provide a phase lock loop design for a digital video interface receiver that is able to track all digital video interface transmitters. Lastly, it is desirable to provide a phase lock loop design for a digital video interface receiver that has an adaptable transfer function so that the phase lock loop design for the digital video interface receiver is able to track all digital video interface transmitters without producing unwanted errors, based upon the differences in transfer functions, and loss of data.